Verilog:Procedural Continuous Assignment to register is not supported

Question

    input [31:0] write_data;
    input [4:0]  write_reg;
    reg [31:0] registers [31:0];

always @(*) 
     assign registers[write_reg] = write_data;

Answer 1

You need to synchronously assign to registers. Because the synthesizer parses it and routes to a physical register (i.e. flip-flop)

always @(posedge clk) 
    my_reg = my_data;