Verilog:Procedural Continuous Assignment to register is not supported

Question

    input [31:0] write_data;
    input [4:0]  write_reg;
    reg [31:0] registers [31:0];

always @(*) 
     assign registers[write_reg] = write_data;

Answer 1

assign inside an always block is the procedural assignment. It is not synthesizable and should not be used. It is there for very special modeling cases.

continuous assignment, or assign outside the always block is there for connecting nets and used all over the places. lhs of such an assignment must be a net type, i.e. wire. it cannot be a reg.

On the other hand all lhs in always blocks must be of 'reg' type.

what you had to do in your case was to remove the keyword assign:

input [31:0] write_data;
input [4:0]  write_reg;
reg [31:0] registers [31:0];

always @(*) 
     registers[write_reg] = write_data;