Making a 4-bit ALU from several 1-bit ALUs

Question

I\'m trying to combine several 1 bit ALUs into a 4 bit ALU. I am confused about how to actually do this in VHDL. Here is the code for the 1bit ALU that I am using:

Answer 1

Interesting you would even ask that question. VHDL synthesizers are quite capable of inferring any adder you like. You can just type what you need:

use ieee.numeric_std.all;
...
signal r : unsigned(3 downto 0);
signal a : unsigned(2 downto 0);
signal b : unsigned(2 downto 0);
signal c : unsigned(2 downto 0);
...
r  <=  a + b + c;

Then you can slice r to fit your needs:

result  <=  std_logic_vector(r(2 downto 0));