What is multiple constant driver error in VHDL

Question

I am developing a VHDL program for flash interface. While compiling my program I got this error.

(clickable)

As you can see in the picture, two signal

Answer 1

Are you doing something like this?

ENTITY test IS
  PORT ( sig1, sig3 : IN BIT;
         sig2 : OUT BIT);
END test;
---------------------------
ARCHITECTURE test_arch of test is
BEGIN
  PROCESS(sig1)
  BEGIN
    sig2 <= '0';
  END process;

  PROCESS(sig3)
  BEGIN
    sig2 <= '1';
  END process;
END test_arch;

Let us test this code:

ghdl -a test.vhd
ghdl -e test
ghdl -r test

we get this error:

sig2
./test:error: several sources for unresolved signal
for signal: .test(test_arch).ghdl: compilation error

This is similar to the one you have posted above and it's come up because my code assigns a value to sig2 in two different processes. How could this be implemented into a circuit?

Maybe there is a workaround, I have not provided a solution to your problem since I don't know how your code looks like.