The states in this FSM machine are changing too quickly due to an issue with the clock updating the present state

Question

I\'m in the process of implementing a finite state machine in verilog, and I\'ve encountered an issue. However, I know what the problem is, but I\'m not sure how to fix it.

Answer 1

If the button input is coming a switch rather than test stimulus it will be asynchronous and so should be put through 2 meta-stability flip-flops. To change one state per button press create an edge detection.

Edge detection will create a 1 clock period wide pulse, resulting in 1 transition per press.

reg [2:0] btn0_meta;
always @(posedge clk or negedge rstN) begin
  if (~rstN) begin
    btn0_meta <= 'b0;
  end
  else begin
    btn0_meta <= {btn0_meta[1:0], btn[0]};
  end
end

reg btn0_posedge;
always @* begin
  btn0_posedge = btn0_meta[1] & ~btn_meta[2]; 
end

Do this for all button inputs and use the btnX_posedge in your state machine.