Adding 2 std_logic_vector in variable type VHDL

Question

I\'m working in this school project. I have two std_logic_vector (31 downto 0) A and B, and I have a variable type std_logic_vector (32 downto 0) and I want to add A+B and put t

Answer 1

First of all you've included the standard library numeric_std and the nonstandard library std_logic_arith together. They conflict with each other so get rid of std_logic_arith.

Both of those packages implement arithmetic using the unsigned and signed types. It is strongly recommend that you use these types if you want to do arithmetic on vectors. It makes it explicitly clear that you want them interpreted in a numeric context. There is no "+" operator defined for the std_logic_vector type implemented in std_logic_1164 which is why you get an error. You can augment that type with arithmetic operators in VHDL-2008 by also including numeric_std_unsigned. Again, it is better to just use the traditional unsigned type:

A : in unsigned(31 downto 0);
B : in unsigned(31 downto 0);

...

process(AluOp)
  variable temp : unsigned(32 downto 0);
begin

  temp := resize(A, temp'length) + B;

The length of the left and right sides of the assignment have to match so first resize the A signal, expanding it to 33 bits before adding the 32-bit signal B.