I am a vhdl begginner, and in need of help for my problem. I have 2 signals that i need to monitor. One is CHECK and the other OK. Every time i ask for a CHECK, I should get
This is a pretty standard state machine, and most designers will use from one to three processes for a state machine. If you are just starting out then using three processes may make things easier for you. The processes would be:
Note that the first two processes are purely combinational logic while the third is a clocked, sequential process.