Making a clock divider

Question

I found this code in how to make a clock divider. I have a general understanding on how to make a divider using counters but i not sure what this code is doing and why its doing

Answer 1

What the above code does is simply that it creates a VHDL module containing a 24 bit counter q, which is counted up on each rising edge from the master clock mclk. It then derives clk190 and clk48 by using different bits of this counter directly as clock signals.

For instance, with mclk at 50 MHz, the lsb (q(0)), would effectively run at 25 MHz. Each rising edge of mclk gives you one edge on q(0) - similarly upwards, so that each subsequent bit runs at half the frequency of the previous bit.

For instance:

mclk = 50 MHz
q(0) = mclk / 2 = 25 Mhz
q(1) = q(0) / 2 = mclk / 4 = 12.5 MHz
...
q(n) = mclk / (2^(n+1))

Your derived clocks will thus be depend on your master clock, and be:

q(17) = 50 MHz / 262144 = 191 Hz
q(19) = 50 MHz / 1048576 = 48 Hz

However - generating clocks like this is often the wrong way to do it!

It may seem as if you get nice synchronized clocks, but in reality, they'll be slightly skewed compared to each other, since you're generating what is known as a gated clock (many tools will even warn you about this).

More info on that here, including a way of doing the same thing (but better) with clock enables: VHDL: creating a very slow clock pulse based on a very fast clock