Verilog Loop Condition

Question

I am completely new to verilog and I have to know quite a bit of it fairly soon for a course I am taking in university. So I am play around with my altera DE2 board and quartis2

Answer 1

Title

Error (10119): Verilog HDL Loop Statement error at : loop with non-constant loop condition must terminate within iterations Description

This error may appear in the Quartus® II software when synthesis iterates through a loop in Verilog HDL for more than the synthesis loop limit. This limit prevents synthesis from potentially running into an infinite loop. By default, this loop limit is set to 250 iterations.

Workaround / Fix

To work around this error, the loop limit can be set using the VERILOG_NON_CONSTANT_LOOP_LIMIT option in the Quartus II Settings File (.qsf). For example:

set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 300