Reading OUT ports for debugging

Question

I have a FIFO which has an interface that looks something like this:

entity fifo is
    port (
    CLK               : IN  std_logic := \'0\';
    DIN                    


        

Answer 1

You have to assign the fifo output to a local signal you can read, then assign that signal to the output (or assign them both in parallel):

DBG_FIFO_OUT <= (your logic here);
DOUT         <= DBG_FIFO_OUT;

or

DBG_FIFO_OUT <= (your logic here);
DOUT         <= (your logic here);