How to NOT use while() loops in verilog (for synthesis)?

Question

I\'ve gotten in the habit of developing a lot testbenches and use for() and while() loops for testing purpose. Thats fine. The problem is that I\'ve taken this habit over to cod

Answer 1

You need to have a clock to control it to start.

always @(posedge clk or negedge rst_n)
  if (!rst_n)
     num <= 32'b0; // or whatever your width is.
  else
     if (num < test_number)
       num <= num + 1'b1;