Verilog Blocking Assignment

Question

I am somewhat new to Verilog. I know that in a Clock Process we should use non blocking assignments, and in a Non Clock processes, we use blocking assignments.

I have c

Answer 1

As others have said, changing to blocking assignments here will actually not work. Using blocking assignments in combinational always blocks (which is the recommendation) require you to put assignments in the right order.

Using non-blocking assignments in combinational always blocks may seem attractive, because you can then have assignments in any order, like in VHDL. Besides performance, one good reason to avoid this is that it doesn't work with always_comb. This code does not work:

always_comb begin
  tmp <= in;
  out <= tmp;
end

The reason is that tmp will not be part of the sensitivity list. It will work as expected if you use always @(*), always @(tmp, in) or replace with blocking assignments.