Verilog Blocking Assignment

Question

I am somewhat new to Verilog. I know that in a Clock Process we should use non blocking assignments, and in a Non Clock processes, we use blocking assignments.

I have c

Answer 1

The blocking vs non-blocking is so that your gate level (synthesis) matches your RTL simulation. Using a different one to alter the behaviour of the simulation as far as I know will not effect synthesis and therefore the behaviour of gate-level.

<= non-blocking effectively take a temporary copy of the copy right-hand side, and make the = blocking assignment at the end of the timestep.

a <= b;
b <= a;

is equivalent to:

a_temp = b;
b_temp = a;
//
a = a_temp;
b = b_temp;

The example uses combinatorial logic, that is it contains no state, so all inputs must be defined by all outputs.

always@* begin
  iowrb_int <= iowrb_met;
  iordb_int <= iordb_met;
  iowrb_met <= iowr_bar;
  iordb_met <= iord_bar;
end

When the right hand side updates the block should be retriggered. Since iowrb_met is on both sides I am not sure what this implies interms of electrical connectivity.

while <= implies copying to a temp location, combinatorial logic does not have this capability, it is always and continuously driven by the assignment.

I think in simulation you effectively have this:

always@* begin
  iowrb_int_temp = iowrb_met;
  iordb_int_temp = iordb_met;
  iowrb_met      = iowr_bar;
  iordb_met      = iord_bar;
  iowrb_int      = iowrb_int_temp;
  iordb_int      = iordb_int_temp;
end

In hardware you would have:

always@* begin
  iowrb_int = iowrb_met;  //= iowr_bar;
  iordb_int = iordb_met;  //= iord_bar;
  iowrb_met = iowr_bar;
  iordb_met = iord_bar;
end

Where iowrb_int is effectively the same as iowrb_met

Flip-flops are implied using always @(posedge clk
Combinatorial logic is implied using always @* but latches can be implied when the output is not fully defined from inputs.