Use a generic to determine (de)mux size in VHDL?

Question

I want to use a generic \'p\' to define how many outputs a demux will have. Input and all outputs are 1 bit. The outputs, control, and input can be something simple like:<

Answer 1

No generics required:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity demux is
    port(
        control : in unsigned;
        input   : in std_logic;
        outputs : out std_logic_vector
        );
end entity demux;

architecture rtl of demux is
    -- Check size of input vectors
    assert 2**control'length = outputs'length 
           report "outputs length must be 2**control length" 
           severity failure;
    -- actually do the demuxing - this will cause feedback latches to be inferred
    outputs(to_integer(unsigned(control)) <= input;

end architecture;

(Untested, just typed in off the top of my head...)

This will infer latches though - is that what you want?