VHDL synthesis warning FF/Latch has a constant value of 0

Question

I\'m trying out some code that essentially involves using an FPGA and reading values from a temperature sensor.

The code is below:

library IEEE;
use          


        

Answer 1

dear same problem i am facing same problem running my code on fir, i have run your code it synthesis but due to warning it show's undefined values of your input and clk, don't assign 0 value, try to put different value like write_temp 7 to 1. i am not full expert of vhdl but when i make this change similar way i get over these warning, hope this work for you also.