VHDL entity and architecture design

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暗喜
暗喜 2021-01-19 05:55

With Ada I can split my modular units into specification and body with .ads and .adb files.

Is it possible to separate VHDL entity and architecture? If so, is ther

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  •  南方客
    南方客 (楼主)
    2021-01-19 06:53

    Entity and architecture are separate design units. They can be in the same file or they can be in separate files. The file extensions remain the same: usually .vhd but .vhdl is also possible. For the file names, there is no generally accepted naming convention. (There are hundreds of conventions really, so that is as useful as no convention at all) Anything works; as an example, you could use myEntity.vhd and myEntity_RTL.vhd.

    You can compile entities and architectures that you write in your own library. You might use your company name as library name.

    Don't confuse libraries with packages, though! A package is a compilation unit that holds reusable declarations. A library is a named set of compilation units.

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