Substatemachine

Question

I have a FSM with 5 states. 3 of them are designed via sub-FSM(UML Pattern). For implementation in VHDL there are 2 ways, imho, to do that:

1. Summarize them

Answer 1

One good solution is to build 2 FSMs:
- the main FSM and
- the sub-FSM(s).

Both FSMs communicate via a handshake protocol.

For example the main FSM enters state TWO. While doing so, the sub-FSM starts its processing, triggered by a signal from main-FSM. When FSM TWO completes, it triggers an signal back to the main FSM, which goes to state TREE.

Using this "pattern" allows you to connect as many FSMs as needed. Some tasks like waiting or address counting can be outsourced into counters, which are just special FSMs.