What does the ? do in Verilog?
For ex: what does that mean of the following command?
input first_din; input [7:0] din; output [12
3条回答 借酒劲吻你 (楼主) 2021-01-15 22:25 Similar to ? : Operator in C, this operator works as simple if else block. b = exp. a ? value_1 : value_2 equals to if ( exp. a )//if true b = value_1; else b = value_2; 0 讨论(0) 查看其它3个回答 发布评论: 提交评论 加载中... 自定义标题段落格式字体字号代码语言点击上传x 验证码 看不清? 提交回复
Similar to ? : Operator in C, this operator works as simple if else block.
b = exp. a ? value_1 : value_2
equals to
if ( exp. a )//if true b = value_1; else b = value_2;
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