Verilog HDL ? operator

Question

What does the ? do in Verilog?

For ex: what does that mean of the following command?

input first_din;
input  [7:0]   din;
output [12         


        

Answer 1

Similar to ? : Operator in C, this operator works as simple if else block.

 b  =  exp. a   ?   value_1  :  value_2

equals to

if ( exp. a )//if true
    b = value_1;
else 
    b = value_2;