Verilog HDL ? operator

Question

What does the ? do in Verilog?

For ex: what does that mean of the following command?

input first_din;
input  [7:0]   din;
output [12         


        

Answer 1

In this code, ? is part of the "Conditional operator" (?:). Refer to the free IEEE Std 1800-2012, Table 11-1—Operators and data types. It is used to model a multiplexer. In your case, first_din is the select, and 8'b0 and parity[127:120] are the data inputs.