Makefile: no rule to make target

Question

I was looking for a solution on this site and also tried google for some time now, but somehow I can\'t get it to work.

My source should be in the src directory and

Answer 1

So finally I found the answer on how to write this makefile, for an exaplanation of my mistakes look at the posting I marked as correct answer:

The resulting makefile looks like this, and for completeness I post it here including dependencies for header files (remove the ASM parts if you don't need 'em):

.SUFFIXES:
.SUFFIXES: .o .cpp
.SUFFIXES: .o .d

CC := g++
LNK:= ar
CXXFLAGS =  -O2 -g -Wall -fmessage-length=0

OBJDIR:=        obj
SRCDIR:=        src
HDIR:=      include

INCLUDE_PATHS:= -Iinclude -Iinclude/interfaces -Iinclude/support

CPP_FILES := propertyfile/propertyfile.cpp \
            propertyfile/propertyitem.cpp \
            propertyfile/propertyfactory.cpp

OBJ :=  $(patsubst %.cpp,$(OBJDIR)/%.o, $(CPP_FILES))
SRC :=  $(patsubst %.cpp,$(SRCDIR)/%.o, $(CPP_FILES))
ASM :=      $(patsubst %.cpp, $(OBJDIR)/$*.asm, $(CPP_FILES))

LIBS:=      

TARGET:=    libsupport.a

all:    $(TARGET)

$(TARGET):  $(OBJ)
    @echo "Linking..."
    @$(LNK) rvs $(TARGET) $(OBJ)
    @cp $(TARGET) ../lib
    @cp -r include ..

clean:
    rm -f $(OBJ) $(ASM) $(TARGET)

-include $(patsubst %.cpp,$(OBJDIR)/%.d, $(CPP_FILES))

$(OBJDIR)/%.o: $(SRCDIR)/%.cpp $(OBJDIR)/%.d 
    @mkdir -p `dirname $@`
    $(CC) $(CXXFLAGS) -S $< -o $(OBJDIR)/$*.asm $(INCLUDE_PATHS)
    $(CC) $(CXXFLAGS) -c $< -o $@ $(INCLUDE_PATHS)

$(OBJDIR)/%.d: $(SRCDIR)/%.cpp 
    $(CC) $(CXXFLAGS) -MM -MT $@ -MF $(OBJDIR)/$*.d -c $< $(INCLUDE_PATHS)  

I hope this helps other user. All examples that I found were either extremly simple and listed multiple files individually and not part of a rule, but didn't really explain how it works, or were so complicated that I couldn't find out how it can help me.