Verilog multiple drivers

Question

I\'m trying to make BCD Counter using Verilog that will be connected to 7-segment decoder.
After I synthesize it, the error occured like this:

Answer 1

Just to add to mcleod_ideafix's answer you have this block:

always @(posedge Clock) begin
  if (Clear) begin
    BCD1 <= 0;
    BCD0 <= 0;
    end
end

Which implies a synchronous clear, I am not sure if that is your intention as typically you would have an asynchronous clear for you flip-flops in ASIC design, or set initial state for FPGA.

For a flip-flop with an asynchronous active-high clear

always @(posedge clock or posedge clear) begin
  if (clear) begin
    BCD1 <= 'b0;  //NB: defined widths
    BCD0 <= 'b0;
  end
  else
    // normal logic
  end
end

It is more typical to use active-low resets:

always @(posedge clock or negedge clear_n) begin
  if (~clear_n) begin
    BCD1 <= 'b0;  //NB: defined widths
    BCD0 <= 'b0;
  end
  else
    if (up == 1'b1) begin
      // up logic
    end
    else if (down == 1'b1) begin
      // down logic
    end
    else begin 
      // nothing to see here
    end
  end
end

Doing comparisons with == 1'b1 means you will get a width mismatch warning instead of weird behaviour if the LHS (left hand side) is wider than 1 bit.

I also noticed that you have:

output [3:0] BCD1_1, BCD0_0 );
reg [3:0] BCD1, BCD0;
assign BCD1_1 = BCD1;
assign BCD0_0 = BCD0;

You just needed to do the following to have reg's as outputs:

output reg [3:0] BCD1, BCD0

Although I find the following much clearer:

output reg [3:0] BCD1,
output reg [3:0] BCD0