Using FOR loop in VHDL with a variable

Question

Is there any possible way to create a for loop in the form:

for i in 0 to some_var loop
    // blah,blah
end loop;

If not, is there any alt

Answer 1

Only loop parameters with static range are synthesizable.

You can implement a FSM(finite state machine) if some_var has a discrete range. Then write a specific loop for each state.