I\'d have some code that needs to be run as the result of a particular interrupt going off.
I don\'t want to execute it in the context of the interrupt itself but I
What you are asking for is pretty straightforward on the Cortex-M3. You need to enable the STIR register so you can trigger the low priority ISR with software. When the high-priority ISR gets done with the critical stuff, it just triggers the low priority interrupt and exits. The NVIC will then tail-chain to the low-priority handler, if there is nothing more important going on.