Does SFENCE prevent the Store Buffer hiding changes from MESI?

Question

If a Core writes but the cache line is not present in its L1, so it writes to the Store Buffer. Another Core requests that cache line, MESI cannot see the Store Buffer updat

Answer 1

As stated in the previous answers, stores will (eventually) become globally visible on other cores in the order they're issued (program order). 'Eventually' is the key, as SFENCE enforces a literal fence on the cycle when the store buffer is drained and the writes on the buffer are made 'globally visibe'.

So, yes, SFENCE instructions cause data in the store buffer to be drained to the cache. This is explained in Section 11.10 of the software developer's manual (SDM).

The SFENCE instruction is also described as:

This serializing operation guarantees that every store instruction that precedes the SFENCE instruction in program order becomes globally visible before any store instruction that follows the SFENCE instruction.

Reads passing writes in the buffer is irrelevant in this context.