Way to initialize synthesizable 2D array with constant values in Verilog

Question

in VHDL, I can easily do this:

constant    cmdbytes       : bytearray(0 to Total) := (x\"05\", x\"00\", x...};

I want synthesizable constan

Answer 1

Does this work?

reg [31:0] array2d[3:0]
....
array2d[3:0] = {{32'd0}};

or

array2d[3:0] = {32'd0, 32'd0, 32'd0, 32'd0}