Handling parameterization in SystemVerilog packages

Question

SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parame

Answer 1

You could use parameterized macros to name a type with particular widths:

`define SIMPLE_STRUCT(NAME) \
   simple_struct_t_``NAME``

`define SIMPLE_STRUCT_DEF(NAME, ADDR_MSB, DATA_MSB) \
 typedef struct { \
        logic [ADDR_MSB``:0] address; \
        logic [DATA_MSB:0] data; \
    } `SIMPLE_STRUCT(NAME)

Then, in some place in your code, you can define the structure(s) you need:

`SIMPLE_STRUCT_DEF(narrow, 7, 31)
`SIMPLE_STRUCT_DEF(wide, 15, 63)

And, then use it wherever you need it, using only the name:

`SIMPLE_STRUCT(narrow) narrow1, narrow2;
narrow1.data = 0;
narrow2 = narrow1;
...