Who is refreshing hardware watchdog in Linux?

Question

I have a processor AT91SAM9G20 running a 2.6 kernel. Watchdog is enabled at bootstrap level and configured for 16 seconds. Watchdog mode register can be configured only once

Answer 1

we had a similar problem regarding WDT on AT91SAM9263. Problem was with bit 29 WDIDLEHLT of WDT_MR (Address: 0xFFFFFD44) register. This bit was set to 1 but it should be 0 for our application needs.

Bit explanation from datasheet documentation:

• WDIDLEHLT: Watchdog Idle Halt

1. 0: The Watchdog runs when the system is in idle mode.
2. 1: The Watchdog stops when the system is in idle state.

This means that WDT counter does not increment when kernel is in idle state, hence the 15 or more delay until reset happens.

You can try "dd if=/dev/zero of=/dev/null" which will prevent kernel from entering idle state and you should get a reset in 16 seconds (or whatever period you have set in WDT_MR register).

So, the solution is to update u-boot code or other piece of code that sets WDT_MR register. Remember this register is write once...