How to write an integer to stdout as hexadecimal in VHDL?

Question

I can print an integer as decimal to stdout with:

library std;
use std.textio.all;

entity min is
end min;

architecture behav of min is
begin
    p         


        

Answer 1

You could use the hwrite procedure in the IEEE.std_logic_textio package:

library IEEE;                                                   -- ADDED
use IEEE.std_logic_1164.all;                                    -- ADDED
use IEEE.numeric_std.all;                                       -- ADDED
use IEEE.std_logic_textio.all;                                  -- ADDED

library std;
use std.textio.all;

entity min is
end min;

architecture behav of min is
begin
    process is
        variable my_line : line;
    begin
        hwrite(my_line, std_logic_vector(to_unsigned(16,8)));   -- CHANGED
        writeline(output, my_line);
        wait;
    end process;
end behav;

The hwrite procedure writes a std_logic_vector to a file. So, you do have to convert your integer into a std_logic_vector, however (which also needs you to specify a number of bits in the to_unsigned function).

http://www.edaplayground.com/x/exs