Proper method for wildcard targets in GNU Make

Question

I am trying to write a Makefile with my source and object files separated and I can\'t seem to figure out the proper way to accomplish this. I have two methods that work but I\'

Answer 1

Your first example is almost there:

SRC = $(wildcard src/*.cpp)
OBJ = $(patsubst src/%.cpp, obj/%.o, $(SRC))

prog: $(OBJ)
  $(CC) $(CFLAGS) $(LDFLAGS) $(LIBS) $(OBJ) -o prog 

obj/%.o: src/%.cpp
  $(CC) $(CFLAGS) -c $< -o $@