How are interrupts handled on SMP?

Question

How are interrupts handled on SMP (Symmeteric multiprocessor/multicore) machines? Is there only one memory management unit or more?

Say two threads, A and B running on d

Answer 1

Each processor has its own memory management unit with a translation lookaside buffer. This is necessary because each core could be executing a different process which has a different address space.

The multiple cores can independently handle interrupts/exceptions at the same time. So there can be multiple concurrent interrupt contexts executing in a kernel at the same time.

An exception such as a page fault or division by zero will always be handled on the same processor on which it occured, since it pertains to what that processor is doing.

External interrupts typically go through some kind of switching fabric that allows them to be mapped to processors in some way, statically or dynamically. E.g. the "APIC" on PC type hardware.

If the fabric is sufficiently sophisticated, then interrupts can be reprogrammed target a different core on the fly.

It depends on the architecture. A simplistic architecture could, for instance, tie all external interrupts to one core. That would not be very symmetric though; it would not allow for IRQ load balancing.

(Also note that it's useful to have certain external interrupts happen on all processors. An example of this is the timer interrupt. If every core has its own interrupt timer, then handling time slicing in the scheduler is symmetric: there is no special case handling for one main core versus the others. An interrupt goes off, the core runs the scheduler code, and if the current task's time quantum is up, it chooses another task to run on that core.)