When L1 misses are a lot different than L2 accesses… TLB related?

Question

I have been running some benchmarks on some algorithms and profiling their memory usage and efficiency (L1/L2/TLB accesses and misses), and some of the results are quite intrigu

Answer 1

The write policy of a data cache determines whether a store hit writes its data only on that cache (write-back or copy-back) or also at the following level of the cache hierarchy (write-through). Hence, a store that hits at a write-through L1-D cache, also writes its data at the L2 cache.

This could be another source of L2 accesses that do not come from L1 cache misses.