VHDL: Is there a convenient way to assign ascii values to std_logic_vector?

Question

• In verilog, I can assign a string to a vector like:

  wire [39:0] hello;
  assign hello = \"hello\"; 
  

• In VHDL, I\'m having diffic

Answer 1

In your example you are trying to assign a string type to a std_logic_vector type. That is simply not allowed. VHDL is strongly typed.

SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0); ... hello <= "hello";

If your goal is to convert from hexa to ascii for printing simulation result you can simply do that:

character'val(to_integer(unsigned(my_std_logic_vector)))