How to sign-extend a number in Verilog

Question

I\'m working on a simple sign-extender in Verilog for a processor I\'m creating for Computer Architecture.

Here\'s what I\'ve got so far: [EDIT: Changed the selection st

Answer 1

We can use the syntax $signed to sign extend

module signextender(
  input [7:0] unextended,//the msb bit is the sign bit
  input clk,
  output reg [15:0] extended 
);

always@(posedge clk)
  begin 
    extended <= $signed(unextended);
  end
endmodule