How to sign-extend a number in Verilog

Question

I\'m working on a simple sign-extender in Verilog for a processor I\'m creating for Computer Architecture.

Here\'s what I\'ve got so far: [EDIT: Changed the selection st

Answer 1

You nearly got it...

always @( posedge clk ) begin
    extended[15:0] <= { {8{extend[7]}}, extend[7:0] };
end

You're also missing a clock edge for the '40' test. Try this, & let me know how you get on...