What is a 'make target'?

Question

Why do I need to make a make target before being able to build my source code?

More specifically, what is make target exactly?

Answer 1

Makefiles look like this:

all: mybinary

mybinary: files.o it.o depends.o on.o
[tab]$(CC) $(CFLAGS) files.o it.o depends.o on.o -o mybinary

files.o: files.c files.h
[tab]$(CC) -c $(CPPFLAGS) $(CFLAGS) $< -o $@

...

This means, when you type make all (the shorthand is just to type make), it will make sure that the mybinary target or file is up to date. To do that, it needs to make sure that mybinary is newer than all of files.o it.o depends.o and on.o. If not, then it uses the shell commands specified on the next line to build mybinary. But before doing that, it first makes sure that files.o and so on are up to date. This means they have to be newer than files.c and files.h. If not, then it uses the shell commands specified on the next line to build files.o. Once all the *.o files are up to date, it can build mybinary. Once mybinary is built, the all target is satisfied.

Targets are usually just files. The format of a block is:

target: list of dependency files
[tab]shell commands to build target if it's older than any of its dependencies
[tab]more shell commands
[tab]still more

Targets can also be specified using wildcards, for instance %.c means what in the shell you'd call *.c.

Some targets are "phony" targets meaning they don't correspond to any real file. The "all" target is of this sort. So too is the "clean" target (make clean). And so on. You don't really need or want to build a file called "all" or "clean". There are various ways to specify that a target is phony.

The first target to appear in the Makefile is the one that will be invoked if you simply type make. One convention is to name this target "all". So then make will be the same as make all.