Disabling the STM32 IWDG during debugging

Question

I have a ChibiOS 3.x program on a STM32F4 microcontroller where I use the IWDG watchdog to reset the MCU on errors like this:

Answer 1

The STM32 MCUs contain a feature called debug freeze. You can stop several peripherals, including I2C timeouts, the RTC and, of course, the watchdog.

In the STM32 reference manual, refer to section 38.16.4ff.

The IWDG is running on the APB1 bus. Therefore you need to modify DBGMCU_APB1_FZ, most specifically assert the bit DBG_IWDG_STOP in that register.

The POR value (= default value) for this register is 0x0, i.e. if you not actively disable it, the IWDG will still be running.

int main() {
    // Disable IWDG if core is halted
    DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_IWDG_STOP;
    // Now we can enable the IWDG
    iwdgInit();
    iwdgStart(&IWDGD, &wd_cfg);
    // [...]
}

Note that when not enabling the watchdog in software, it might still be enabled in hardware if the WDG_SW bit is reset in the flash option bytes.

If you are using the ST HAL (not included in ChibiOS, see STM32CubeF4), you can also use this macro:

 __HAL_DBGMCU_FREEZE_IWDG();

(which basically does exactly the same as we did above)

Besides, you need enable the DBGMCU clock on APB2 before calling __HAL_DBGMCU_FREEZE_IWDG().

 __HAL_RCC_DBGMCU_CLK_ENABLE();