Demand Paging: Calculating effective memory access time

Question

I can\'t understand the answer to this question:

Consider an OS using one level of paging with TLB registers. If the page fault rate is 10% and dirty pages should be rel

Answer 1

reading the question I was thinking about a more realistic scenario based, for instance, on a two-level paging system.

In this scenario, as far as I can understand, there could be the case page table (PT) itself is not resident in memory (PT itself may have been paged out from RAM into swapping area (e.g. Linux) or into pagefile (e.g. Windows)).

Regarding page directory (the first level of paging hierarchy) I believe it has to be always resident in RAM (otherwise, upon context switch, the x86 CR3 register content would be totally useless...)

Thus it exist a percentage of occurrences we have to include at least:

• Disk access time needed to read & bring in memory (from swapping area or pagefile) the PT itself
• MEM time needed to access PT now in memory

Does it make sense ?