Is initialization necessary?

Question

In VHDL, is initialization necessary when creating a signal or a vector? What happens if one forgets to initialize a signal or integer value?

Answer 1

In simulation, if you do not set an initial value, each element of your vector will get the default value (this is defined by the VHDL language specification). For enum types, this is the first element defined in the enumeration type: booleans will be false, std_logic will be 'U' (undefined). Note that 'U' has no meaning in electrical circuits. It is merely a hint for the verification engineer that you don't know which value the flip-flop has at power-on.

After synthesis: FPGA synthesizers will use the initial value that you set as the "power on" value of the flip-flops and memories if the target technology supports this! If the technology does not support a forced initial value (and for ASICs), the initial value at power-on is not known. It could be 1 or 0. (See for example: http://quartushelp.altera.com/11.0/mergedProjects/hdl/vhdl/vhdl_pro_power_up_state.htm)

Two possible styles:

1. Choose an explicit initial value, with or without explicit reset circuits (usually for modern FPGAs)
2. Set 'U' as initial value, and have a proper reset circuit to force a known reset value

If you go with the first choice, be sure to check if your target technology supports this style!