I\'m using a makefile to compile a program made of many .c files, and any time make is invoked it only compiles those files modified after the last run
.c
make
Another solution (one which I like because it's flexible)
ifeq ("$(BUILD_VERBOSE)","1") Q := vecho = @echo else Q := @ vecho = @true endif %.o: %.c $(vecho) "-> Compiling $@" $(Q)$(CC) $(CFLAGS) -c $< -o $@
You can skip the vecho stuff, but it does come in handy at times.